{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11264402","patent":{"patent_number":"US-11264402","title":"Boundary design to reduce memory array edge CMP dishing effect","assignee":null,"inventors":[],"filing_date":"2019-11-26T00:00:00.000Z","publication_date":"2022-03-01T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":20,"abstract":"In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of memory devices within an embedded memory region of a substrate and forming a plurality of transistor devices within a logic region of the substrate. A first isolation structure is formed within a boundary region of the substrate disposed between the logic region and the embedded memory region. The first isolation structure is formed within a recess in the substrate. A logic wall is formed over the first isolation structure. The logic wall surrounds the embedded memory region and has a first height that is greater than heights of the plurality of memory devices."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Boundary design to reduce memory array edge CMP dishing effect","description":"In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of memory devices within an embedded memory region of a substrate","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11264402","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11264402","citation_suggestion":"Patentable. \"Boundary design to reduce memory array edge CMP dishing effect\" (US-11264402). https://patentable.app/patents/US-11264402","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11264402","json":"https://patentable.app/api/llm-context/US-11264402","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T13:14:10.502Z"}