{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11269528","patent":{"patent_number":"US-11269528","title":"Data storage device with reduced memory access operation method thereof and controller therefor","assignee":null,"inventors":[],"filing_date":"2019-11-06T00:00:00.000Z","publication_date":"2022-03-08T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":12,"abstract":"A data storage device may include: a memory array comprising a plurality of blocks, each block including a plurality of pages and a controller in communication with the memory array and comprising a memory buffer, the controller configured to maintain attribute information associated with each block and each page of the memory array, the controller further configured to read data from a requested page in the memory array responsive to an external request, store the read data in a first region of the memory buffer to output the read data responsive to the external request, and copy the read data from the first region of the memory buffer into a second region of the memory buffer upon a determination based on the attribute information that the requested page is included in a supposed-to-be-erased region."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Data storage device with reduced memory access operation method thereof and controller therefor","description":"A data storage device may include: a memory array comprising a plurality of blocks, each block including a plurality of pages and a controller in communication with the memory array and comprising a m","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11269528","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11269528","citation_suggestion":"Patentable. \"Data storage device with reduced memory access operation method thereof and controller therefor\" (US-11269528). https://patentable.app/patents/US-11269528","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11269528","json":"https://patentable.app/api/llm-context/US-11269528","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T05:37:58.846Z"}