{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11270768","patent":{"patent_number":"US-11270768","title":"Failure prevention of chip power network","assignee":null,"inventors":[],"filing_date":"2020-03-04T00:00:00.000Z","publication_date":"2022-03-08T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","H01L","H01L","H01L","G11C","G11C","G11C"],"num_claims":20,"abstract":"A semiconductor structure is provided. The structure includes a RRAM cell having a first end and a second end. The second end is connected to a first potential. The structure includes a decoupling capacitor having a first end connected in series with the first end of the RRAM cell and a second end connected to a second potential. The structure includes a FET arranged across the capacitor to form a bridged capacitor by having a FET source connected to the first end of the capacitor and a FET drain connected to the second end of the capacitor. A paired activation and subsequent deactivation of the FET enables a short protection mode of the capacitor that provides a series resistance above a threshold amount, between the second potential and the first end of the RRAM cell, responsive to a detected short of the capacitor from the supply to the first potential."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Failure prevention of chip power network","description":"A semiconductor structure is provided. The structure includes a RRAM cell having a first end and a second end. The second end is connected to a first potential. The structure includes a decoupling cap","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11270768","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11270768","citation_suggestion":"Patentable. \"Failure prevention of chip power network\" (US-11270768). https://patentable.app/patents/US-11270768","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11270768","json":"https://patentable.app/api/llm-context/US-11270768","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T20:31:00.694Z"}