{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11271042","patent":{"patent_number":"US-11271042","title":"Via resistance reduction","assignee":null,"inventors":[],"filing_date":"2018-03-16T00:00:00.000Z","publication_date":"2022-03-08T00:00:00.000Z","cpc_codes":["G11C","H01L","H01L","H01L","H01L"],"num_claims":18,"abstract":"One embodiment provides a method of making a memory device. The method includes forming a via in a bit line, an interlayer and a dielectric region. The bit line is formed on the interlayer. The interlayer is formed partially on the dielectric region and partially on a plurality of memory cells. The via has a first end included in, and in direct contact with, the bit line and a second end to couple to an electrical contact."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Via resistance reduction","description":"One embodiment provides a method of making a memory device. The method includes forming a via in a bit line, an interlayer and a dielectric region. The bit line is formed on the interlayer. The interl","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11271042","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11271042","citation_suggestion":"Patentable. \"Via resistance reduction\" (US-11271042). https://patentable.app/patents/US-11271042","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11271042","json":"https://patentable.app/api/llm-context/US-11271042","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T22:13:19.842Z"}