{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11271089","patent":{"patent_number":"US-11271089","title":"Method for manufacturing semiconductor structure with unleveled gate structure","assignee":null,"inventors":[],"filing_date":"2019-10-29T00:00:00.000Z","publication_date":"2022-03-08T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":20,"abstract":"Methods for forming the semiconductor structure are provided. The method includes forming a fin structure and forming a gate dielectric layer across the fin structure. The method includes forming a work function metal layer over the gate dielectric layer and forming a gate electrode layer over the work function metal layer. The method further includes etching the work function metal layer to form a gap and etching the gate dielectric layer to enlarge the gap. The method further includes etching the gate electrode layer from the enlarged gap and forming a dielectric layer covering the gate dielectric layer, the work function metal layer, and the gate electrode layer. In addition, the dielectric layer includes a first portion, a second portion, and a third portion, and the first portion is thicker than the second portion, and the second portion is thicker than the third portion."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for manufacturing semiconductor structure with unleveled gate structure","description":"Methods for forming the semiconductor structure are provided. The method includes forming a fin structure and forming a gate dielectric layer across the fin structure. The method includes forming a wo","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11271089","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11271089","citation_suggestion":"Patentable. \"Method for manufacturing semiconductor structure with unleveled gate structure\" (US-11271089). https://patentable.app/patents/US-11271089","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11271089","json":"https://patentable.app/api/llm-context/US-11271089","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T18:34:31.799Z"}