{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11275402","patent":{"patent_number":"US-11275402","title":"Read clock generation circuit and data processing circuit including the same","assignee":null,"inventors":[],"filing_date":"2019-11-25T00:00:00.000Z","publication_date":"2022-03-15T00:00:00.000Z","cpc_codes":["G06F","G06F","G11C","G11C","G06F","G06F","G06F","G06F","G06F"],"num_claims":11,"abstract":"A read clock generation circuit may include a multiplexer selecting one of divided clock signals in response to a selection signal and outputting the selected divided clock signal as a preliminary read clock signal, a detection circuit generating a detection signal for indicating detection timing of a divided clock signal having the fastest second edge after the first edge of a write clock signal, among the divided clock signals, based on a result of a comparison between the phases of the divided clock signals and the phase of the write clock signal, a counter generating the selection signal by counting the detection signal in response to the write clock signal, and a correction circuit outputting, as a read clock signal, a signal from which pulses corresponding to an invalid section have been removed, among the pulses of the preliminary read clock signal, in response to the detection signal."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Read clock generation circuit and data processing circuit including the same","description":"A read clock generation circuit may include a multiplexer selecting one of divided clock signals in response to a selection signal and outputting the selected divided clock signal as a preliminary rea","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11275402","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11275402","citation_suggestion":"Patentable. \"Read clock generation circuit and data processing circuit including the same\" (US-11275402). https://patentable.app/patents/US-11275402","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11275402","json":"https://patentable.app/api/llm-context/US-11275402","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T21:13:24.410Z"}