{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11276477","patent":{"patent_number":"US-11276477","title":"Memory controller and operating method thereof","assignee":null,"inventors":[],"filing_date":"2020-10-26T00:00:00.000Z","publication_date":"2022-03-15T00:00:00.000Z","cpc_codes":["G11C","G06F","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":17,"abstract":"A memory controller performs an efficient error correction operation. The memory controller controls a memory device. The memory controller includes: an error corrector configured to perform one or more error correction operations to correct an error included in data read from the memory device during a read operation, the one or more error correction operations including a first error correction operation performed using a first read voltage determined based on a threshold voltage distribution obtained by assuming that a number of memory cells in an erase state is equal to a number of memory cells in a program state and a data controller in communication with the error corrector to receive first error correction data obtained from the first error correction operation and configured to store the first error correction data in the memory controller."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory controller and operating method thereof","description":"A memory controller performs an efficient error correction operation. The memory controller controls a memory device. The memory controller includes: an error corrector configured to perform one or mo","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11276477","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11276477","citation_suggestion":"Patentable. \"Memory controller and operating method thereof\" (US-11276477). https://patentable.app/patents/US-11276477","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11276477","json":"https://patentable.app/api/llm-context/US-11276477","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T20:58:10.982Z"}