{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11281795","patent":{"patent_number":"US-11281795","title":"Hierarchical random scrambling of secure data storage resulting in randomness across chips and on power on resets of individual chips","assignee":null,"inventors":[],"filing_date":"2019-12-24T00:00:00.000Z","publication_date":"2022-03-22T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":23,"abstract":"A system includes a random number generator generating a random number in response to an event. Control logic generates hierarchical part alignment selectors from the random number. For each secure data block to be stored in volatile storage, a physical address of a first logical address for that secure data block is set based upon the hierarchical part alignment selectors. For each data word within that secure data block, a physical address of a first logical address for that data word is set based upon the hierarchical part alignment selectors. For each data byte within that data word, a physical address of a first logical address for that data byte is set based upon the hierarchical part alignment selectors. A physical address of a logical address for a first data bit within that data byte is set based upon the hierarchical part alignment selectors."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Hierarchical random scrambling of secure data storage resulting in randomness across chips and on power on resets of individual chips","description":"A system includes a random number generator generating a random number in response to an event. Control logic generates hierarchical part alignment selectors from the random number. For each secure da","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11281795","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11281795","citation_suggestion":"Patentable. \"Hierarchical random scrambling of secure data storage resulting in randomness across chips and on power on resets of individual chips\" (US-11281795). https://patentable.app/patents/US-11281795","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11281795","json":"https://patentable.app/api/llm-context/US-11281795","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T21:24:47.083Z"}