{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11282753","patent":{"patent_number":"US-11282753","title":"Method of simultaneously forming contacts to a power rail and the source and drain regions of a FinFET","assignee":null,"inventors":[],"filing_date":"2019-01-21T00:00:00.000Z","publication_date":"2022-03-22T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":6,"abstract":"In a method for manufacturing a semiconductor device that comprises a semiconductor fin including a source region and a drain region, which configure a field effect transistor, and a fixed potential line provided in parallel to the semiconductor fin, the method comprises: a first step of preparing an intermediate body in which an insulating layer is provided on the source region (P-type conductive region), the drain region (N-type conductive region), and the fixed potential line; and a second step of simultaneously forming contact holes leading to the source region, the drain region, and the fixed potential line, in the insulating layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of simultaneously forming contacts to a power rail and the source and drain regions of a FinFET","description":"In a method for manufacturing a semiconductor device that comprises a semiconductor fin including a source region and a drain region, which configure a field effect transistor, and a fixed potential l","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11282753","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11282753","citation_suggestion":"Patentable. \"Method of simultaneously forming contacts to a power rail and the source and drain regions of a FinFET\" (US-11282753). https://patentable.app/patents/US-11282753","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11282753","json":"https://patentable.app/api/llm-context/US-11282753","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T13:27:34.267Z"}