{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11282828","patent":{"patent_number":"US-11282828","title":"High density architecture design for 3D logic and 3D memory circuits","assignee":null,"inventors":[],"filing_date":"2020-08-19T00:00:00.000Z","publication_date":"2022-03-22T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L"],"num_claims":20,"abstract":"Techniques herein include methods of forming higher density circuits by combining multiple substrates via stacking and bonding of individual substrates. High voltage and low voltage devices along with 3D NAND devises are fabricated on a first wafer, and high voltage and low voltage devices and/or memory are then fabricated on a second wafer and/or third wafer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"High density architecture design for 3D logic and 3D memory circuits","description":"Techniques herein include methods of forming higher density circuits by combining multiple substrates via stacking and bonding of individual substrates. High voltage and low voltage devices along with","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11282828","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11282828","citation_suggestion":"Patentable. \"High density architecture design for 3D logic and 3D memory circuits\" (US-11282828). https://patentable.app/patents/US-11282828","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11282828","json":"https://patentable.app/api/llm-context/US-11282828","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T19:35:41.301Z"}