{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11288011","patent":{"patent_number":"US-11288011","title":"Non-volatile memory array with write failure protection for multi-level cell (MLC) storage elements using coupled writes","assignee":null,"inventors":[],"filing_date":"2020-03-26T00:00:00.000Z","publication_date":"2022-03-29T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":22,"abstract":"Methods and apparatus for use with non-volatile memory (NVM) arrays having single-level cell (SLC) layers and multi-level cell (MLC) layers, such as triple-level cell (TLC) layers, provide for a coupled SLC/MLC write operation where SLC write protection is combined into a MLC write flow. In an illustrative example, data is written concurrently to SLC and TLC. The SLC data provides a backup for the TLC data in the event the TLC data is defective. The TLC data is verified using, for example, write verification. If the data is successfully verified, the SLC block can be erased or otherwise overwritten with new data. If not, the SLC block can be used to recover the data for storage in a different TLC block. The coupled SLC/MLC write operation may be performed in conjunction with a quick pass write (QPW)."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Non-volatile memory array with write failure protection for multi-level cell (MLC) storage elements using coupled writes","description":"Methods and apparatus for use with non-volatile memory (NVM) arrays having single-level cell (SLC) layers and multi-level cell (MLC) layers, such as triple-level cell (TLC) layers, provide for a coupl","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11288011","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11288011","citation_suggestion":"Patentable. \"Non-volatile memory array with write failure protection for multi-level cell (MLC) storage elements using coupled writes\" (US-11288011). https://patentable.app/patents/US-11288011","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11288011","json":"https://patentable.app/api/llm-context/US-11288011","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T10:39:39.085Z"}