{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11288207","patent":{"patent_number":"US-11288207","title":"Apparatus and method for processing address translation and invalidation transactions","assignee":null,"inventors":[],"filing_date":"2020-03-30T00:00:00.000Z","publication_date":"2022-03-29T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":17,"abstract":"Apparatus comprises address translation circuitry configured to access translation data defining a set of memory address translations; transaction handling circuitry to receive translation transactions and to receive invalidation transactions, each translation transaction defining one or more input memory addresses in an input memory address space to be translated to respective output memory addresses in an output memory address space, in which the transaction handling circuitry is configured to control the address translation circuitry to provide the output memory address as a translation response; in which each invalidation transaction defines at least a partial invalidation of the translation data; transaction tracking circuitry to associate an invalidation epoch, of a set of at least two invalidation epochs, with each translation transaction and with each invalidation transaction; and invalidation circuitry to store data defining a given invalidation transaction and, for translation transactions having the same invalidation epoch as the given invalidation transaction and handled by the address translation circuitry subsequent to the invalidation circuitry storing the data defining the given invalidation transaction, to process those translation transactions to indicate that a translation transaction is invalidated when the invalidation defined by the given invalidation transaction applies to that translation transaction; the invalidation circuitry being configured to forward at least an acknowledgement of the invalidation transaction for further processing by other apparatus in response to storage of the data by the invalidation circuitry."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Apparatus and method for processing address translation and invalidation transactions","description":"Apparatus comprises address translation circuitry configured to access translation data defining a set of memory address translations; transaction handling circuitry to receive translation transaction","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11288207","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11288207","citation_suggestion":"Patentable. \"Apparatus and method for processing address translation and invalidation transactions\" (US-11288207). https://patentable.app/patents/US-11288207","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11288207","json":"https://patentable.app/api/llm-context/US-11288207","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T08:27:59.018Z"}