{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11289141","patent":{"patent_number":"US-11289141","title":"Integrated circuit with asymmetric arrangements of memory arrays","assignee":null,"inventors":[],"filing_date":"2020-02-18T00:00:00.000Z","publication_date":"2022-03-29T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"An integrated circuit includes a first array of memory cells, a second array of memory cells, a first pair of complementary data lines, a second pair of complementary data lines, and a third pair of complementary data lines. The first pair of complementary data lines extend along the first array of memory cells, and are coupled to the first array of memory cells. The second pair of complementary data lines extend along the second array of memory cells, and are coupled to the first pair of complementary data lines. The third pair of complementary data lines extend along the second array of memory cells, and are coupled to the second array of memory cells. A number of rows of memory cells in the first array of memory cells is different from a number of rows of memory cells in the second array of memory cells."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Integrated circuit with asymmetric arrangements of memory arrays","description":"An integrated circuit includes a first array of memory cells, a second array of memory cells, a first pair of complementary data lines, a second pair of complementary data lines, and a third pair of c","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11289141","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11289141","citation_suggestion":"Patentable. \"Integrated circuit with asymmetric arrangements of memory arrays\" (US-11289141). https://patentable.app/patents/US-11289141","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11289141","json":"https://patentable.app/api/llm-context/US-11289141","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T09:43:20.998Z"}