{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11289448","patent":{"patent_number":"US-11289448","title":"Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops","assignee":null,"inventors":[],"filing_date":"2020-04-22T00:00:00.000Z","publication_date":"2022-03-29T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":23,"abstract":"A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops","description":"A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; an","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11289448","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11289448","citation_suggestion":"Patentable. \"Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops\" (US-11289448). https://patentable.app/patents/US-11289448","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11289448","json":"https://patentable.app/api/llm-context/US-11289448","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T14:27:27.005Z"}