{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11289571","patent":{"patent_number":"US-11289571","title":"Semiconductor apparatus for reducing parasitic capacitance","assignee":null,"inventors":[],"filing_date":"2020-07-07T00:00:00.000Z","publication_date":"2022-03-29T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":22,"abstract":"The present invention provides a diode chip, including: a semiconductor chip, including a p-type first semiconductor layer and an n-type second semiconductor layer formed on the first semiconductor layer; a first pad separation trench, formed on the semiconductor chip in a manner of penetrating the second semiconductor layer till reaching the first semiconductor layer, and forming a first internal parasitic capacitance between the first semiconductor layer and the second semiconductor layer by separating a portion of the semiconductor chip from other regions; an inter-insulation layer, covering the second semiconductor layer; and a first electrode layer, being opposite to the region separated by the first pad separation trench with the inter-insulation layer interposed in between, and forming, between the first electrode layer and the semiconductor chip, a first external parasitic capacitance connected in series to the first internal parasitic capacitance."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor apparatus for reducing parasitic capacitance","description":"The present invention provides a diode chip, including: a semiconductor chip, including a p-type first semiconductor layer and an n-type second semiconductor layer formed on the first semiconductor la","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11289571","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11289571","citation_suggestion":"Patentable. \"Semiconductor apparatus for reducing parasitic capacitance\" (US-11289571). https://patentable.app/patents/US-11289571","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11289571","json":"https://patentable.app/api/llm-context/US-11289571","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T18:02:45.218Z"}