{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11290115","patent":{"patent_number":"US-11290115","title":"Low latency combined clock data recovery logic network and charge pump circuit","assignee":null,"inventors":[],"filing_date":"2019-06-12T00:00:00.000Z","publication_date":"2022-03-29T00:00:00.000Z","cpc_codes":["G06F","H04L"],"num_claims":20,"abstract":"Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, applying the sequence of data decisions and the error signal to each logic branch of a set of logic branches, and responsively selecting a logic branch from the set of logic branches, the logic branch selected responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch generating an output current, and providing the output current to a local oscillator controller, the output current sourcing and sinking current to a capacitor through a resistive element to adjust an input voltage of a proportional control circuit relative to a voltage on the capacitor connected to the resistive element."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Low latency combined clock data recovery logic network and charge pump circuit","description":"Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11290115","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11290115","citation_suggestion":"Patentable. \"Low latency combined clock data recovery logic network and charge pump circuit\" (US-11290115). https://patentable.app/patents/US-11290115","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11290115","json":"https://patentable.app/api/llm-context/US-11290115","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T11:53:01.939Z"}