{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11295797","patent":{"patent_number":"US-11295797","title":"Techniques to mitigate asymmetric long delay stress","assignee":null,"inventors":[],"filing_date":"2020-11-24T00:00:00.000Z","publication_date":"2022-04-05T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C"],"num_claims":25,"abstract":"Methods, systems, and devices for techniques to mitigate asymmetric long delay stress are described. A memory device may activate a memory cell during a first phase of an access operation cycle. The memory device may write a first state or a second state to the memory cell during the first phase of the access operation cycle. The memory device may maintain the first state or the second state during a second phase of the access operation cycle after the first phase of the access operation cycle. The memory device may write, during a third phase of the access operation cycle after the second phase of the access operation cycle, the second state to the memory cell. The memory device may precharge the memory cell during the third phase of the access operation cycle based on writing the second state to the memory cell."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Techniques to mitigate asymmetric long delay stress","description":"Methods, systems, and devices for techniques to mitigate asymmetric long delay stress are described. A memory device may activate a memory cell during a first phase of an access operation cycle. The m","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11295797","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11295797","citation_suggestion":"Patentable. \"Techniques to mitigate asymmetric long delay stress\" (US-11295797). https://patentable.app/patents/US-11295797","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11295797","json":"https://patentable.app/api/llm-context/US-11295797","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T12:44:57.111Z"}