{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11295991","patent":{"patent_number":"US-11295991","title":"Complementary cell circuits employing isolation structures for defect reduction and related methods of fabrication","assignee":null,"inventors":[],"filing_date":"2020-02-24T00:00:00.000Z","publication_date":"2022-04-05T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":20,"abstract":"To prevent short defects between source/drains of transistors of a complementary cell circuit, isolation walls are formed in an isolation region between the source/drains of the transistors prior to growing a P-type epitaxial layer and an N-type epitaxial layer on respective sides of the isolation region. The isolation walls provide a physical barrier to prevent formation of short defects that can otherwise form between the P-type and N-type epitaxial layers. Thus, the isolation walls prevent circuit failures resulting from electrical shorts between source/drain regions of transistors in complementary cell circuits. A width of the isolation region between a P-type transistor and an N-type transistor in a circuit cell layout can be reduced so that a total layout area of the complementary cell circuit can be reduced without reducing product yield. A gate cut may be formed in the dummy gate with a process of forming the isolation walls."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Complementary cell circuits employing isolation structures for defect reduction and related methods of fabrication","description":"To prevent short defects between source/drains of transistors of a complementary cell circuit, isolation walls are formed in an isolation region between the source/drains of the transistors prior to g","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11295991","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11295991","citation_suggestion":"Patentable. \"Complementary cell circuits employing isolation structures for defect reduction and related methods of fabrication\" (US-11295991). https://patentable.app/patents/US-11295991","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11295991","json":"https://patentable.app/api/llm-context/US-11295991","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T07:47:19.040Z"}