{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11296032","patent":{"patent_number":"US-11296032","title":"Silicon interposer including through-silicon via structures with enhanced overlay tolerance and methods of forming the same","assignee":null,"inventors":[],"filing_date":"2020-05-28T00:00:00.000Z","publication_date":"2022-04-05T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"An array of through-silicon via (TSV) structures is formed through a silicon substrate, and package-side metal pads are formed on backside surfaces of the array of TSV structures. The silicon substrate is disposed over a carrier substrate, and an encapsulant interposer frame, such as an epoxy molding compound (EMC) interposer frame is formed around the silicon substrate. A die-side redistribution structure is formed over the silicon substrate and the EMC interposer frame, and at least one semiconductor die is attached to the die-side redistribution structure. The carrier substrate is removed from underneath the package-side metal pads. A package-side redistribution structure is formed on the package-side metal pads and on the EMC interposer frame. Overlay tolerance between the package-side redistribution wiring interconnects and the package-side metal pads increases due to increased areas of the package-side metal pads."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Silicon interposer including through-silicon via structures with enhanced overlay tolerance and methods of forming the same","description":"An array of through-silicon via (TSV) structures is formed through a silicon substrate, and package-side metal pads are formed on backside surfaces of the array of TSV structures. The silicon substrat","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11296032","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11296032","citation_suggestion":"Patentable. \"Silicon interposer including through-silicon via structures with enhanced overlay tolerance and methods of forming the same\" (US-11296032). https://patentable.app/patents/US-11296032","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11296032","json":"https://patentable.app/api/llm-context/US-11296032","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T18:34:36.913Z"}