{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11296083","patent":{"patent_number":"US-11296083","title":"Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) electrically coupled by integrated vertical FET-to-FET interconnects for complementary metal-oxide semiconductor (CMOS) cell circuits","assignee":null,"inventors":[],"filing_date":"2020-03-06T00:00:00.000Z","publication_date":"2022-04-05T00:00:00.000Z","cpc_codes":["H01L","B82Y"],"num_claims":26,"abstract":"3D vertically-integrated FETs electrically coupled by integrated vertical FET-to-FET interconnects for reducing an area of CMOS cell circuits are disclosed. Vertically integrated FETs reduce a footprint area of an integrated circuit chip. The FETs include horizontal channel structures that are vertically integrated by stacking a second channel structure of a second FET above a first channel structure of a first FET. The first and second FETs can include a combination of a PFET and NFET that can be used to form a 3D CMOS cell circuit as an example. The area occupied by the 3D CMOS cell circuit includes interconnects for electrically coupling terminal regions of the FETs internally and externally. Vertical FET-to-FET interconnects extend between the FETs to electrically couple terminal regions of the FETs to reduce a number of vias from a semiconductor layer of the 3D CMOS cell circuit to metal interconnect layers above the vertically-integrated FETs."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) electrically coupled by integrated vertical FET-to-FET interconnects for complementary metal-oxide semiconductor (CMOS) cell circuits","description":"3D vertically-integrated FETs electrically coupled by integrated vertical FET-to-FET interconnects for reducing an area of CMOS cell circuits are disclosed. Vertically integrated FETs reduce a footpri","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11296083","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11296083","citation_suggestion":"Patentable. \"Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) electrically coupled by integrated vertical FET-to-FET interconnects for complementary metal-oxide semiconductor (CMOS) cell circuits\" (US-11296083). https://patentable.app/patents/US-11296083","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11296083","json":"https://patentable.app/api/llm-context/US-11296083","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T13:18:08.848Z"}