{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11296107","patent":{"patent_number":"US-11296107","title":"Channel hole and bitline architecture and method to improve page or block size and performance of 3D NAND","assignee":null,"inventors":[],"filing_date":"2019-05-22T00:00:00.000Z","publication_date":"2022-04-05T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":20,"abstract":"Embodiments of a memory finger structure and architecture for a three-dimensional memory device and fabrication method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate, the alternating layer stack including a plurality of conductor/dielectric layer pairs. The memory device further includes a first column of vertical memory strings extending through the alternating layer stack, and a first plurality of bitlines displaced along a first direction and extending along a second direction. The first column of vertical memory strings is disposed at a first angle relative to the second direction. Each of the first plurality of bitlines is connected to an individual vertical memory string in the first column."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Channel hole and bitline architecture and method to improve page or block size and performance of 3D NAND","description":"Embodiments of a memory finger structure and architecture for a three-dimensional memory device and fabrication method thereof are disclosed. The memory device includes an alternating layer stack disp","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11296107","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11296107","citation_suggestion":"Patentable. \"Channel hole and bitline architecture and method to improve page or block size and performance of 3D NAND\" (US-11296107). https://patentable.app/patents/US-11296107","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11296107","json":"https://patentable.app/api/llm-context/US-11296107","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T14:27:34.109Z"}