{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11301319","patent":{"patent_number":"US-11301319","title":"Memory device and memory system having multiple error correction functions, and operating method thereof","assignee":null,"inventors":[],"filing_date":"2019-09-19T00:00:00.000Z","publication_date":"2022-04-12T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":11,"abstract":"A memory system includes a memory cell array including a first memory area and a second memory area, an input/output circuit including input/output lines for transmitting or receiving data bits and parity bits to or from the first and second memory areas, and an error correction circuit including a plurality of sub error correction circuits including a first sub error correction circuit for performing a first error correction operation on first data bits of the first memory area received through the input/output lines, and a second sub error correction circuit for performing a second error correction operation on second data bits of the second memory area received through the input/output lines. The first memory area has a higher bit error rate than the second memory area."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory device and memory system having multiple error correction functions, and operating method thereof","description":"A memory system includes a memory cell array including a first memory area and a second memory area, an input/output circuit including input/output lines for transmitting or receiving data bits and pa","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11301319","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11301319","citation_suggestion":"Patentable. \"Memory device and memory system having multiple error correction functions, and operating method thereof\" (US-11301319). https://patentable.app/patents/US-11301319","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11301319","json":"https://patentable.app/api/llm-context/US-11301319","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T20:58:51.574Z"}