{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11301408","patent":{"patent_number":"US-11301408","title":"Asymmetric read / write architecture for enhanced throughput and reduced latency","assignee":null,"inventors":[],"filing_date":"2021-06-07T00:00:00.000Z","publication_date":"2022-04-12T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":18,"abstract":"The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit includes a network interface. The integrated circuit also includes a communication bus interface. The integrated circuit is configured to establish a communication link with a processor of the host computing device over the communication bus interface, which includes mapping to memory addresses associated with the processor of the host computing device. The integrated circuit is also configured to receive payload data for transmission over the network interface in response to the processor of the host computing device writing payload data to the mapped memory addresses using one or more programmed input-outputs (PIOs). Further, the integrated circuit is configured to write payload data received over the network interface to the memory of the host computing device using direct memory access (DMA)."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Asymmetric read / write architecture for enhanced throughput and reduced latency","description":"The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit include","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11301408","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11301408","citation_suggestion":"Patentable. \"Asymmetric read / write architecture for enhanced throughput and reduced latency\" (US-11301408). https://patentable.app/patents/US-11301408","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11301408","json":"https://patentable.app/api/llm-context/US-11301408","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T20:32:34.266Z"}