{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11301607","patent":{"patent_number":"US-11301607","title":"Testing of asynchronous reset logic","assignee":null,"inventors":[],"filing_date":"2019-12-18T00:00:00.000Z","publication_date":"2022-04-12T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":20,"abstract":"Testing of integrated circuitry, wherein the integrated circuitry includes a flip-flop with an asynchronous input, so that during performance of asynchronous scan patterns, glitches are avoided. Combinatorial logic circuitry delivers a local reset signal to the asynchronous input independent of an assertion of an asynchronous global reset signal. A synchronous scan test is performed of delivery of the local reset signal from the combinatorial logic circuitry while masking delivery of any reset signal to the asynchronous input of the flip-flop. An asynchronous scan test is performed of an asynchronous reset of the flip-flop with the asynchronous global reset signal while masking delivery of the local reset signal to the asynchronous input of the flip-flop."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Testing of asynchronous reset logic","description":"Testing of integrated circuitry, wherein the integrated circuitry includes a flip-flop with an asynchronous input, so that during performance of asynchronous scan patterns, glitches are avoided. Combi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11301607","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11301607","citation_suggestion":"Patentable. \"Testing of asynchronous reset logic\" (US-11301607). https://patentable.app/patents/US-11301607","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11301607","json":"https://patentable.app/api/llm-context/US-11301607","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T11:13:51.115Z"}