{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11302415","patent":{"patent_number":"US-11302415","title":"Row address comparator for a row redundancy control circuit in a memory","assignee":null,"inventors":[],"filing_date":"2019-12-12T00:00:00.000Z","publication_date":"2022-04-12T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"Disclosed is a row address comparator with voltage level shifting and latching functionality and including: an evaluation section for comparing two row addresses in a first voltage domain and outputting an initial match signal in a second voltage domain; and a latch section for outputting a latched final match signal based on the initial match signal. The comparator employs a first clock signal (CLK1), a second clock signal (CLK2) that is different from CLK1 and a third clock signal (CLK3) that is inverted with respect to CLK2. CLKs 1 and 2 control pre-charge and evaluation operations within the evaluation section with CLK2 being set to minimize hold time. CLKs 2 and 3 control the latch operation within the latch section. Feedback loops in both sections enhance performance. Also disclosed are a control circuit that incorporates the comparator and a method for implementing row redundancy in a memory."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Row address comparator for a row redundancy control circuit in a memory","description":"Disclosed is a row address comparator with voltage level shifting and latching functionality and including: an evaluation section for comparing two row addresses in a first voltage domain and outputti","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11302415","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11302415","citation_suggestion":"Patentable. \"Row address comparator for a row redundancy control circuit in a memory\" (US-11302415). https://patentable.app/patents/US-11302415","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11302415","json":"https://patentable.app/api/llm-context/US-11302415","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T09:44:05.740Z"}