{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11302581","patent":{"patent_number":"US-11302581","title":"Gate profile control through sidewall protection during etching","assignee":null,"inventors":[],"filing_date":"2020-05-05T00:00:00.000Z","publication_date":"2022-04-12T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":20,"abstract":"A method includes depositing a dummy gate dielectric layer over a semiconductor region, depositing a dummy gate electrode layer, and performing a first etching process. An upper portion of the dummy gate electrode layer is etched to form an upper portion of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper portion of the dummy gate electrode, and performing a second etching process. A lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode. A third etching process is then performed to etch the lower portion of the dummy gate electrode using the protection layer as an etching mask. The dummy gate electrode is tapered by the third etching process. The protection layer is removed, and the dummy gate electrode is replaced with a replacement gate electrode."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Gate profile control through sidewall protection during etching","description":"A method includes depositing a dummy gate dielectric layer over a semiconductor region, depositing a dummy gate electrode layer, and performing a first etching process. An upper portion of the dummy g","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11302581","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11302581","citation_suggestion":"Patentable. \"Gate profile control through sidewall protection during etching\" (US-11302581). https://patentable.app/patents/US-11302581","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11302581","json":"https://patentable.app/api/llm-context/US-11302581","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T14:38:55.980Z"}