{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11303281","patent":{"patent_number":"US-11303281","title":"Efficient pipelined architecture for superconducting single flux quantum logic circuits utilizing dual clocks","assignee":null,"inventors":[],"filing_date":"2021-04-05T00:00:00.000Z","publication_date":"2022-04-12T00:00:00.000Z","cpc_codes":["G06N","G06N","G06N"],"num_claims":31,"abstract":"An SFQ circuit system includes at least one SFQ block having a plurality of SFQ logic gates. Characteristically, at least a portion of the SFQ logic gates are arranged in series. The SFQ circuit system includes a timing system configured to provide a first set of inputs and collect a first set of outputs of the at least one SFQ block at a rate defined by a slow clock frequency while the SFQ logic gates are clocked at a fast clock frequency. Advantageously, the rate is sufficiently slow to allow the first set of inputs to propagate through all levels of the SFQ logic gates to produce the first set of outputs of the at least one SFQ block without colliding with a second set of inputs to the at least one SFQ block."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Efficient pipelined architecture for superconducting single flux quantum logic circuits utilizing dual clocks","description":"An SFQ circuit system includes at least one SFQ block having a plurality of SFQ logic gates. Characteristically, at least a portion of the SFQ logic gates are arranged in series. The SFQ circuit syste","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11303281","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11303281","citation_suggestion":"Patentable. \"Efficient pipelined architecture for superconducting single flux quantum logic circuits utilizing dual clocks\" (US-11303281). https://patentable.app/patents/US-11303281","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11303281","json":"https://patentable.app/api/llm-context/US-11303281","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T14:10:25.664Z"}