{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11307767","patent":{"patent_number":"US-11307767","title":"System for controlling memory operations in system-on-chips","assignee":null,"inventors":[],"filing_date":"2020-10-15T00:00:00.000Z","publication_date":"2022-04-19T00:00:00.000Z","cpc_codes":["G06F","G11C","G06F","G06F","G11C","G11C","G11C"],"num_claims":20,"abstract":"A system-on-chip (SoC) includes a system memory, a memory controller, and a memory management system coupled therebetween. The memory management system is configured to receive, from the memory controller, a first control signal that is indicative of a memory operation associated with the system memory, and output and provide a second control signal to the system memory to control an execution of the memory operation. The second control signal is outputted such that when the memory operation corresponds to a first read operation, the first read operation is executed with the system memory, and when the memory operation corresponds to a first write operation, a second read operation is executed with the system memory followed by the first write operation. Thus, the memory management system prevents memory corruption of the system memory when an asynchronous reset event is detected in the SoC."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"System for controlling memory operations in system-on-chips","description":"A system-on-chip (SoC) includes a system memory, a memory controller, and a memory management system coupled therebetween. The memory management system is configured to receive, from the memory contro","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11307767","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11307767","citation_suggestion":"Patentable. \"System for controlling memory operations in system-on-chips\" (US-11307767). https://patentable.app/patents/US-11307767","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11307767","json":"https://patentable.app/api/llm-context/US-11307767","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T09:44:13.335Z"}