{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11307779","patent":{"patent_number":"US-11307779","title":"System and method for flash and RAM allocation for reduced power consumption in a processor","assignee":null,"inventors":[],"filing_date":"2020-08-13T00:00:00.000Z","publication_date":"2022-04-19T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":16,"abstract":"The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"System and method for flash and RAM allocation for reduced power consumption in a processor","description":"The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RA","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11307779","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11307779","citation_suggestion":"Patentable. \"System and method for flash and RAM allocation for reduced power consumption in a processor\" (US-11307779). https://patentable.app/patents/US-11307779","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11307779","json":"https://patentable.app/api/llm-context/US-11307779","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T16:46:38.176Z"}