{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11461531","patent":{"patent_number":"US-11461531","title":"Learning-based analyzer for mitigating latch-up in integrated circuits","assignee":null,"inventors":[],"filing_date":"2019-04-29T00:00:00.000Z","publication_date":"2022-10-04T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06N","G06N","G06N","G06N","G06F","G06F","G06F","G06N","G06N","G06N"],"num_claims":20,"abstract":"Systems and methods related to learning-based analyzers (both supervised and unsupervised) for mitigating latch-up in integrated circuits are provided. An example method includes obtaining latch-up data concerning at least one integrated circuit configured to operate under a range of temperature conditions, where the at least one integrated circuit comprises a core portion including at least a plurality of devices each having one or more structural features formed using a lithographic process, and an input/output portion. The method further includes training the learning-based system based on training data derived from the latch-up data and a first layout rule concerning a first spacing between the core portion and the input/output portion. The method further includes using the learning-based system generating a second layout rule concerning the first spacing between the core portion and the input/output portion, where the second layout rule is different from the first layout rule."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Learning-based analyzer for mitigating latch-up in integrated circuits","description":"Systems and methods related to learning-based analyzers (both supervised and unsupervised) for mitigating latch-up in integrated circuits are provided. An example method includes obtaining latch-up da","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11461531","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11461531","citation_suggestion":"Patentable. \"Learning-based analyzer for mitigating latch-up in integrated circuits\" (US-11461531). https://patentable.app/patents/US-11461531","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11461531","json":"https://patentable.app/api/llm-context/US-11461531","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T05:38:35.589Z"}