{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11462510","patent":{"patent_number":"US-11462510","title":"Stacked package structure and stacked packaging method for chip","assignee":null,"inventors":[],"filing_date":"2020-06-26T00:00:00.000Z","publication_date":"2022-10-04T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A stacked package structure for a chip, can include: a substrate having a first surface and a second surface opposite thereto; a first die having an active and back faces, where the active face of the first die includes pads; a first enclosure that covers the first die; an interlinkage that extends to the first enclosure to electrically couple with the pads; a first redistribution body electrically coupled to the interlinkage, and being partially exposed on a surface of the stacked package structure to provide outer pins for electrically coupling to external circuitry; a penetrating body that penetrates the first enclosure and substrate; a second die having an electrode electrically coupled to a first terminal of the penetrating body; and a second terminal of the penetrating body that is exposed on the surface of the stacked package structure to provide outer pins for electrically coupling to the external circuitry."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Stacked package structure and stacked packaging method for chip","description":"A stacked package structure for a chip, can include: a substrate having a first surface and a second surface opposite thereto; a first die having an active and back faces, where the active face of the","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11462510","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11462510","citation_suggestion":"Patentable. \"Stacked package structure and stacked packaging method for chip\" (US-11462510). https://patentable.app/patents/US-11462510","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11462510","json":"https://patentable.app/api/llm-context/US-11462510","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T03:22:23.528Z"}