{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11468934","patent":{"patent_number":"US-11468934","title":"Access line disturbance mitigation","assignee":null,"inventors":[],"filing_date":"2021-01-07T00:00:00.000Z","publication_date":"2022-10-11T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"Methods, systems, and devices for access line disturbance mitigation are described to, for example, reduce voltage disturbances on deselected digit lines during a read or write operation. Memory cells of a memory device may be couplable with a write circuit including a level shifter circuit, such that changes in voltage on a selected digit line may be controlled via a level shifter circuit of a write circuit associated with a selected memory cell. The write circuit may write a logic state to the memory cell after completing a read operation. One or more write voltages may be applied to or removed from the memory cell via the level shifter circuit, which may control a slew rate of one or more voltage changes on the selected digit line. The slew rate(s) may be controlled via a current driver circuit coupled with a pull-up circuit or a pull-down circuit of the level shifter circuit."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Access line disturbance mitigation","description":"Methods, systems, and devices for access line disturbance mitigation are described to, for example, reduce voltage disturbances on deselected digit lines during a read or write operation. Memory cells","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11468934","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11468934","citation_suggestion":"Patentable. \"Access line disturbance mitigation\" (US-11468934). https://patentable.app/patents/US-11468934","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11468934","json":"https://patentable.app/api/llm-context/US-11468934","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:31:42.345Z"}