{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11474939","patent":{"patent_number":"US-11474939","title":"Memory device for improving speed of cache read operation and method of operating the same","assignee":null,"inventors":[],"filing_date":"2020-10-29T00:00:00.000Z","publication_date":"2022-10-18T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":18,"abstract":"The present technology relates to a memory device and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells, a data register connected to the memory cell array through a bit line and configured to store data sensed through the bit line, a cache register configured to cache the data stored in the data register, and a control logic configured to control a caching operation of receiving a cache read command from a memory controller and storing the data, which is stored in the data register, in the cache register, during a cache read period, in response to the cache read command, wherein the control logic controls the caching operation based on whether the cache read command is a first command received after receiving a normal read command from the memory controller."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory device for improving speed of cache read operation and method of operating the same","description":"The present technology relates to a memory device and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells, a data register connected to","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11474939","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11474939","citation_suggestion":"Patentable. \"Memory device for improving speed of cache read operation and method of operating the same\" (US-11474939). https://patentable.app/patents/US-11474939","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11474939","json":"https://patentable.app/api/llm-context/US-11474939","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T21:24:53.712Z"}