{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11475933","patent":{"patent_number":"US-11475933","title":"Variation mitigation scheme for semi-digital mac array with a 2T-2 resistive memory element bitcell","assignee":null,"inventors":[],"filing_date":"2020-04-14T00:00:00.000Z","publication_date":"2022-10-18T00:00:00.000Z","cpc_codes":["G11C","G06F","G06F","G11C","G11C","G11C","G06N"],"num_claims":18,"abstract":"A method, system and electronic device for mitigating variance in a two transistor two resistive memory element (2T2R) circuit is provided. The method includes calculating a sum of a number of logical 1's in a column of bitcells in the 2T2R circuit, N, of an input vector, sensing output current values from each current line in the column of bitcells and calculating an inner product, M, of the input vector and the bitcells in the column in the 2T2R circuit based on the sensed output current values."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Variation mitigation scheme for semi-digital mac array with a 2T-2 resistive memory element bitcell","description":"A method, system and electronic device for mitigating variance in a two transistor two resistive memory element (2T2R) circuit is provided. The method includes calculating a sum of a number of logical","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11475933","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11475933","citation_suggestion":"Patentable. \"Variation mitigation scheme for semi-digital mac array with a 2T-2 resistive memory element bitcell\" (US-11475933). https://patentable.app/patents/US-11475933","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11475933","json":"https://patentable.app/api/llm-context/US-11475933","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T11:52:18.497Z"}