{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11475935","patent":{"patent_number":"US-11475935","title":"Memory cell arrangement and methods thereof","assignee":null,"inventors":[],"filing_date":"2021-06-08T00:00:00.000Z","publication_date":"2022-10-18T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"Various aspects relate to a memory cell arrangement including: a memory cell including a field-effect transistor structure and a spontaneous-polarizable memory layer; and a control circuit configured to cause a writing of the memory cell by a writing operation, the writing operation including: carrying out a writing sequence including: supplying a write signal set to the memory cell to provide a write voltage drop to bring a threshold voltage of the memory cell into a target range by polarizing the memory layer, and, subsequently, supplying a post-conditioning signal set to the memory cell to provide a post-conditioning voltage drop having opposite polarity with respect to the write voltage drop to change the threshold voltage by partially depolarizing the memory layer; and checking whether the threshold voltage is in the target range, and repeating the writing sequence in the case that the threshold voltage is not in the target range."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory cell arrangement and methods thereof","description":"Various aspects relate to a memory cell arrangement including: a memory cell including a field-effect transistor structure and a spontaneous-polarizable memory layer; and a control circuit configured ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11475935","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11475935","citation_suggestion":"Patentable. \"Memory cell arrangement and methods thereof\" (US-11475935). https://patentable.app/patents/US-11475935","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11475935","json":"https://patentable.app/api/llm-context/US-11475935","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T15:39:36.807Z"}