{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11476214","patent":{"patent_number":"US-11476214","title":"Sidewall spacer to reduce bond pad necking and/or redistribution layer necking","assignee":null,"inventors":[],"filing_date":"2020-12-10T00:00:00.000Z","publication_date":"2022-10-18T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"In some embodiments, an integrated chip (IC) is provided. The IC includes a metallization structure disposed over a semiconductor substrate, where the metallization structure includes an interconnect structure disposed in an interlayer dielectric (ILD) structure. A passivation layer is disposed over the metallization structure, where an upper surface of the interconnect structure is at least partially disposed between opposite inner sidewalls of the passivation layer. A sidewall spacer is disposed along the opposite inner sidewalls of the passivation layer, where the sidewall spacer has rounded sidewalls. A conductive structure is disposed on the passivation layer, the rounded sidewalls of the sidewall spacer, and the upper surface of the interconnect structure."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Sidewall spacer to reduce bond pad necking and/or redistribution layer necking","description":"In some embodiments, an integrated chip (IC) is provided. The IC includes a metallization structure disposed over a semiconductor substrate, where the metallization structure includes an interconnect ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11476214","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11476214","citation_suggestion":"Patentable. \"Sidewall spacer to reduce bond pad necking and/or redistribution layer necking\" (US-11476214). https://patentable.app/patents/US-11476214","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11476214","json":"https://patentable.app/api/llm-context/US-11476214","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T06:33:34.676Z"}