{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11476234","patent":{"patent_number":"US-11476234","title":"Chip package structure and manufacturing method thereof","assignee":null,"inventors":[],"filing_date":"2020-04-13T00:00:00.000Z","publication_date":"2022-10-18T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":12,"abstract":"A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit layer have been formed on the carrier. A flat structure layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and covers the flat structure layer and a portion of the first dielectric layer. A second patterned circuit layer is formed on the second dielectric layer. The second patterned circuit layer includes a plurality of pads. An orthographic projection of the flat structure layer on the carrier overlaps orthographic projections of the pads on the carrier. A plurality of chips are disposed on the pads. A molding compound is formed to cover the second dielectric layer and encapsulate the chips and the pads."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Chip package structure and manufacturing method thereof","description":"A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit laye","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11476234","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11476234","citation_suggestion":"Patentable. \"Chip package structure and manufacturing method thereof\" (US-11476234). https://patentable.app/patents/US-11476234","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11476234","json":"https://patentable.app/api/llm-context/US-11476234","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T02:39:52.283Z"}