{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11476364","patent":{"patent_number":"US-11476364","title":"Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer","assignee":null,"inventors":[],"filing_date":"2021-03-15T00:00:00.000Z","publication_date":"2022-10-18T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":28,"abstract":"An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer","description":"An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11476364","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11476364","citation_suggestion":"Patentable. \"Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer\" (US-11476364). https://patentable.app/patents/US-11476364","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11476364","json":"https://patentable.app/api/llm-context/US-11476364","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T21:46:54.444Z"}