{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11481214","patent":{"patent_number":"US-11481214","title":"Sparse matrix calculations untilizing ightly tightly coupled memory and gather/scatter engine","assignee":null,"inventors":[],"filing_date":"2020-07-14T00:00:00.000Z","publication_date":"2022-10-25T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":31,"abstract":"A processor for sparse matrix calculation can include an on-chip memory, a cache, a gather/scatter engine and a core. The on-chip memory can be configured to store a first matrix or vector, and the cache can be configured to store a compressed sparse second matrix data structure. The compressed sparse second matrix data structure can include: a value array including non-zero element values of the sparse second matrix, where each entry includes a given number of element values; and a column index array where each entry includes the given number of offsets matching the value array. The gather/scatter engine can be configured to gather element values of the first matrix or vector using the column index array of the sparse second matrix. In a horizontal implementation, the gather/scatter engine can be configured to gather sets of element values from different sub-banks within a same row based on the column index array of the sparse matrix. In a vertical implementation, the gather/scatter engine can be configured to gather sets of element values from different rows based on the column index array of the sparse matrix. In a hybrid horizontal/vertical implementation, the gather/scatter engine can be configured to gather sets of element values from sets of rows and from different sub-banks within the same rows based on the column index array of the sparse matrix. The core can be configured to perform sparse matrix-matrix multiplication or sparse-matrix-vector multiplication using the gathered elements of the first matrix or vector and the value array of the compressed sparse second matrix."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Sparse matrix calculations untilizing ightly tightly coupled memory and gather/scatter engine","description":"A processor for sparse matrix calculation can include an on-chip memory, a cache, a gather/scatter engine and a core. The on-chip memory can be configured to store a first matrix or vector, and the ca","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11481214","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11481214","citation_suggestion":"Patentable. \"Sparse matrix calculations untilizing ightly tightly coupled memory and gather/scatter engine\" (US-11481214). https://patentable.app/patents/US-11481214","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11481214","json":"https://patentable.app/api/llm-context/US-11481214","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T06:35:02.766Z"}