{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11482439","patent":{"patent_number":"US-11482439","title":"Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors","assignee":null,"inventors":[],"filing_date":"2021-07-15T00:00:00.000Z","publication_date":"2022-10-25T00:00:00.000Z","cpc_codes":["H01L","G11C","H01L","H01L","H01L","H01L","H01L","B82Y","G11C","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":17,"abstract":"A method for producing a 3D memory device including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one first memory cell is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors","description":"A method for producing a 3D memory device including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors;","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11482439","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11482439","citation_suggestion":"Patentable. \"Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors\" (US-11482439). https://patentable.app/patents/US-11482439","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11482439","json":"https://patentable.app/api/llm-context/US-11482439","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T06:52:11.198Z"}