{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11482508","patent":{"patent_number":"US-11482508","title":"Semiconductor package and manufacturing method thereof","assignee":null,"inventors":[],"filing_date":"2020-07-21T00:00:00.000Z","publication_date":"2022-10-25T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A manufacturing method of a semiconductor package includes the following steps. A chip is provided. The chip has an active surface and a rear surface opposite to the active surface. The chip includes conductive pads disposed at the active surface. A first solder-containing alloy layer is formed on the rear surface of the chip. A second solder-containing alloy layer is formed on a surface and at a location where the chip is to be attached. The chip is mounted to the surface and the first solder-containing alloy layer is aligned with the second solder-containing alloy layer. A reflow step is performed on the first and second solder-containing alloy layers to form a joint alloy layer between the chip and the surface."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor package and manufacturing method thereof","description":"A manufacturing method of a semiconductor package includes the following steps. A chip is provided. The chip has an active surface and a rear surface opposite to the active surface. The chip includes ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11482508","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11482508","citation_suggestion":"Patentable. \"Semiconductor package and manufacturing method thereof\" (US-11482508). https://patentable.app/patents/US-11482508","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11482508","json":"https://patentable.app/api/llm-context/US-11482508","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T02:44:52.161Z"}