{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11487446","patent":{"patent_number":"US-11487446","title":"Overhead reduction in data transfer protocol for NAND memory","assignee":null,"inventors":[],"filing_date":"2021-02-12T00:00:00.000Z","publication_date":"2022-11-01T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G11C","G11C","G11C","G11C","G06F","G06F"],"num_claims":20,"abstract":"A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Overhead reduction in data transfer protocol for NAND memory","description":"A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresse","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11487446","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11487446","citation_suggestion":"Patentable. \"Overhead reduction in data transfer protocol for NAND memory\" (US-11487446). https://patentable.app/patents/US-11487446","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11487446","json":"https://patentable.app/api/llm-context/US-11487446","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T22:14:57.836Z"}