{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11487561","patent":{"patent_number":"US-11487561","title":"Post simulation debug and analysis using a system memory model","assignee":null,"inventors":[],"filing_date":"2014-12-24T00:00:00.000Z","publication_date":"2022-11-01T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F"],"num_claims":29,"abstract":"According to an embodiment, a system and method are provided for constructing an accurate view of memory and events on a simulation platform. The system memory view can be used with a debug and analysis tool to provide post-processing debug, including searching forward and backward in capture time of the stored memory view to analyze the events of the simulation. The memory is constructed by capturing and storing each memory execution transaction, bus transaction, and register transaction during simulation. Changes in simulation platform hardware state may also be captured and stored in a hardware state database, including switches between process threads detected during the simulation that may update a simulator register. The captured events provide observability into the OS processes, the hardware, and the embedded software of the simulation platform."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Post simulation debug and analysis using a system memory model","description":"According to an embodiment, a system and method are provided for constructing an accurate view of memory and events on a simulation platform. The system memory view can be used with a debug and analys","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11487561","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11487561","citation_suggestion":"Patentable. \"Post simulation debug and analysis using a system memory model\" (US-11487561). https://patentable.app/patents/US-11487561","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11487561","json":"https://patentable.app/api/llm-context/US-11487561","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T13:41:49.651Z"}