{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11488557","patent":{"patent_number":"US-11488557","title":"Gate driver on array circuit layout","assignee":null,"inventors":[],"filing_date":"2019-10-30T00:00:00.000Z","publication_date":"2022-11-01T00:00:00.000Z","cpc_codes":["G09G","G09G","G09G","G09G","G09G","G09G","G09G"],"num_claims":13,"abstract":"A gate driver on array (GOA) circuit layout is provided, including a plurality of driving thin-film transistor units, wherein each of the driving thin-film transistor units includes a wiring side and a capacitor side, and any two adjacent driving thin-film transistor units are spaced apart and connected in series with each other; and a plurality of first capacitor areas, wherein each of the first capacitor areas is disposed between two adjacent capacitor sides of the driving thin-film transistor units. The GOA circuit layout according to the present invention increases heat dissipation area for the driving thin-film transistors, which is more advantageous for heat dissipation. On the other hand, because of sufficient use of the first capacitor areas, a size of layout is basically not increased."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Gate driver on array circuit layout","description":"A gate driver on array (GOA) circuit layout is provided, including a plurality of driving thin-film transistor units, wherein each of the driving thin-film transistor units includes a wiring side and ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11488557","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11488557","citation_suggestion":"Patentable. \"Gate driver on array circuit layout\" (US-11488557). https://patentable.app/patents/US-11488557","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11488557","json":"https://patentable.app/api/llm-context/US-11488557","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T16:21:34.844Z"}