{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11488657","patent":{"patent_number":"US-11488657","title":"Fast interval read setup for 3D memory","assignee":null,"inventors":[],"filing_date":"2021-04-19T00:00:00.000Z","publication_date":"2022-11-01T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":18,"abstract":"A memory having a plurality of blocks is coupled with control circuits having logic to execute a no-current read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks while disabling current flow. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include, respectively, a plurality of sub-blocks. The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Fast interval read setup for 3D memory","description":"A memory having a plurality of blocks is coupled with control circuits having logic to execute a no-current read setup operation, the read setup operation comprising simultaneously applying a read set","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11488657","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11488657","citation_suggestion":"Patentable. \"Fast interval read setup for 3D memory\" (US-11488657). https://patentable.app/patents/US-11488657","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11488657","json":"https://patentable.app/api/llm-context/US-11488657","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T18:03:55.118Z"}