{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11488660","patent":{"patent_number":"US-11488660","title":"Adiabatic flip-flop and memory cell design","assignee":null,"inventors":[],"filing_date":"2021-02-19T00:00:00.000Z","publication_date":"2022-11-01T00:00:00.000Z","cpc_codes":["G11C"],"num_claims":2,"abstract":"In a method computer storage element operation, first and second rising (or falling) clock edges are applied to first and second power inputs of the computer storage element having a transistor array between the first and second power inputs over time T1 whereupon a logic value applied to an input of the transistor array is stored therein. Thereafter, first and second falling (or rising) clock edges are applied to the first and second power inputs over time T2, whereupon part of an electrical charge or energy associated with the logic value stored in the transistor array is provided to circuitry that generates the first and/or second clock edge(s), wherein the value(s) of time T1 and/or time T2 is/are greater than a product of RC, where R is resistance associated with the computer storage element, and C is a load capacitance associated with the computer storage element."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Adiabatic flip-flop and memory cell design","description":"In a method computer storage element operation, first and second rising (or falling) clock edges are applied to first and second power inputs of the computer storage element having a transistor array ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11488660","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11488660","citation_suggestion":"Patentable. \"Adiabatic flip-flop and memory cell design\" (US-11488660). https://patentable.app/patents/US-11488660","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11488660","json":"https://patentable.app/api/llm-context/US-11488660","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T07:59:56.623Z"}