{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11488861","patent":{"patent_number":"US-11488861","title":"Method for manufacturing an interconnect structure having a selectively formed bottom via","assignee":null,"inventors":[],"filing_date":"2020-09-11T00:00:00.000Z","publication_date":"2022-11-01T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A method for manufacturing an interconnection structure includes forming a second dielectric layer on a wafer. The wafer includes a first dielectric layer and a conductive element embedded in the first dielectric layer. An opening is formed in the second dielectric layer to expose the conductive element. A dielectric spacer layer is selectively formed to be in contact with surfaces defining the opening of the second dielectric layer. The dielectric spacer layer exposes the conductive element. A bottom via is formed in the opening and in contact with the dielectric spacer layer and the conductive element. A portion of the dielectric spacer layer is removed to form a dielectric spacer in contact with the bottom via. A top via is formed in the opening and over the bottom via and the dielectric spacer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for manufacturing an interconnect structure having a selectively formed bottom via","description":"A method for manufacturing an interconnection structure includes forming a second dielectric layer on a wafer. The wafer includes a first dielectric layer and a conductive element embedded in the firs","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11488861","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11488861","citation_suggestion":"Patentable. \"Method for manufacturing an interconnect structure having a selectively formed bottom via\" (US-11488861). https://patentable.app/patents/US-11488861","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11488861","json":"https://patentable.app/api/llm-context/US-11488861","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T12:25:23.561Z"}