{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11488879","patent":{"patent_number":"US-11488879","title":"Methods and apparatuses to wafer-level test adjacent semiconductor die","assignee":null,"inventors":[],"filing_date":"2020-06-08T00:00:00.000Z","publication_date":"2022-11-01T00:00:00.000Z","cpc_codes":["H01L","H01L","G11C","G11C","G11C","G11C","H01L"],"num_claims":20,"abstract":"Wafer-level testing of multiple adjacent semiconductor die of a semiconductor wafer in parallel using built-in self-test circuitry for a memory (mBIST) and scribe lines that connect certain terminals of a semiconductor die to terminals of an adjacent semiconductor die. During the wafer-level testing, probe needles of a test setup connect to a single one of the multiple adjacent semiconductor die, and mBIST commands are passed from the single one of the multiple adjacent semiconductor die to one or more adjacent semiconductor die. In some examples, the scribe lines connect mBIST circuit terminals of one semiconductor die to mBIST circuit terminals of an adjacent semiconductor die. In some examples, the scribe lines connect I/O terminals of one semiconductor die to I/O terminals of an adjacent semiconductor die. The scribe lines may cross scribe regions of the wafer to connect the respective terminals of the adjacent semiconductor die."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Methods and apparatuses to wafer-level test adjacent semiconductor die","description":"Wafer-level testing of multiple adjacent semiconductor die of a semiconductor wafer in parallel using built-in self-test circuitry for a memory (mBIST) and scribe lines that connect certain terminals ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11488879","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11488879","citation_suggestion":"Patentable. \"Methods and apparatuses to wafer-level test adjacent semiconductor die\" (US-11488879). https://patentable.app/patents/US-11488879","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11488879","json":"https://patentable.app/api/llm-context/US-11488879","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T18:37:32.637Z"}