{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11494087","patent":{"patent_number":"US-11494087","title":"Tolerating memory stack failures in multi-stack systems","assignee":null,"inventors":[],"filing_date":"2018-10-31T00:00:00.000Z","publication_date":"2022-11-08T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"Memory management circuitry and processes operate to improve reliability of a group of memory stacks, providing that if a memory stack or a portion thereof fails during the product's lifetime, the system may still recover with no errors or data loss. A front-end controller receives a block of data requested to be written to memory, divides the block into sub-blocks, and creates a new redundant reliability sub-block. The sub-blocks are then written to different memory stacks. When reading data from the memory stacks, the front-end controller detects errors indicating a failure within one of the memory stacks, and recovers corrected data using the reliability sub-block. The front-end controller may monitor errors for signs of a stack failure and disable the failed stack."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Tolerating memory stack failures in multi-stack systems","description":"Memory management circuitry and processes operate to improve reliability of a group of memory stacks, providing that if a memory stack or a portion thereof fails during the product's lifetime, the sys","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11494087","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11494087","citation_suggestion":"Patentable. \"Tolerating memory stack failures in multi-stack systems\" (US-11494087). https://patentable.app/patents/US-11494087","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11494087","json":"https://patentable.app/api/llm-context/US-11494087","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T10:34:44.618Z"}