{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11494542","patent":{"patent_number":"US-11494542","title":"Semiconductor device, method of generating layout diagram and system for same","assignee":null,"inventors":[],"filing_date":"2020-01-13T00:00:00.000Z","publication_date":"2022-11-08T00:00:00.000Z","cpc_codes":["G06F","H01L","G06F","G06F","H01L"],"num_claims":20,"abstract":"A semiconductor device includes: an active area in a transistor layer; contact-source/drain (CSD) conductors in the transistor layer; gate conductors in the transistor layer, and interleaved with the CSD conductors; VG structures in the transistor layer, and over the active area; and a first gate-signal-carrying (GSC) conductor in an M_1st layer that is over the transistor layer, and that is over the active area; and wherein long axes correspondingly of the active area and the first GSC conductor extend substantially in a first direction; and long axes correspondingly of the CSD conductors and the gate conductors extend substantially in a second direction, the second direction being substantially perpendicular to the first direction."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor device, method of generating layout diagram and system for same","description":"A semiconductor device includes: an active area in a transistor layer; contact-source/drain (CSD) conductors in the transistor layer; gate conductors in the transistor layer, and interleaved with the ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11494542","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11494542","citation_suggestion":"Patentable. \"Semiconductor device, method of generating layout diagram and system for same\" (US-11494542). https://patentable.app/patents/US-11494542","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11494542","json":"https://patentable.app/api/llm-context/US-11494542","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T07:59:47.069Z"}